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參數(shù)資料
| 型號： | MC68HC05K3DWR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 128/132頁 |
| 文件大?。?/td> | 1188K |
| 代理商： | MC68HC05K3DWR2 |
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Personality EEPROM (PEEPROM)
Serial Data Readout Sequence
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
Personality EEPROM (PEEPROM)
95
9.8 Serial Data Readout Sequence
The read sequence of the internal personality EEPROM always begins
at bit address 00 of the 128-bit array. The signal timing on the IRQ and
PB0 pins is shown in Figure 9-7. The personality EEPROM can be
serially read out by using this sequence:
1. Follow the serial programming mode entry routine as specified in
2. Keep the DATA signal at 0 Vdc.
3. Clock the SEL/CLK signal line to 0 Vdc and back to VSELCKH (first
select bit).
4. Clock the SEL/CLK signal line to 0 Vdc and back to VSELCKH
(second select bit).
5. Raise the DATA signal line to VDDS.
6. Clock the SEL/CLK signal line to 0 Vdc and back to VSELCKH (third
select bit).
7. The device is now ready to transmit the data that has been
programmed or erased into the 128 bits of the personality
EEPROM. During the next 128 clocks of the SEL/CLK signal line,
the stored data for each bit (starting with location $00) is
presented on the DATA signal line prior to the falling edge of the
SEL/CLK signal line to 0 Vdc. The data is valid within tDRV internal
cycles after the rising edge of SEL/CLK and is valid when the
SEL/CLK signal line falls for a time, tHIZ.
8. On the 128th data bit, rather than drive the SEL/CLK signal low to
complete the read sequence, drive the RESET pin to 0 V. This
must be done to prevent the part from entering an unknown state.
If all 128 bits do not need to be verified, the RESET pin may be
driven to 0 V after the last bit has been verified.
9. While RESET is held low, the pins can be conditioned for the next
sequence.
This completes the serial data readout sequence, and the device can
now be completely erased by going to the bulk erase sequence if the
verification sequence fails to read the desired data.
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