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參數(shù)資料
| 型號(hào)： | MC68HC05K3DWR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 73/132頁 |
| 文件大?。?/td> | 1188K |
| 代理商： | MC68HC05K3DWR2 |
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Interrupts
Hardware Interrupts
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
Interrupts
45
service routine located at the address specified by the contents of $03FA
and $03FB.
Entering the interrupt service routine automatically clears the IRQ latch.
The IRQ interrupt service routine also may clear the IRQ latch by writing
a logic 1 to the IRQR acknowledge bit in the ISCR. As long as the output
state of the IRQF flag bit is active, the CPU continuously re-enters the
IRQ interrupt sequence following an RTI instruction until the active state
is removed or the IRQE enable bit is cleared.
4.6.2 IRQ Status/Control Register
The IRQ interrupt function is controlled by the IRQ status/control register
(ISCR) located at $000A as shown in Figure 4-4. All unused bits in the
ISCR read as logic 0s. A reset clears the IRQF bit and sets the IRQE
bit.
IRQR — IRQ Interrupt Acknowledge Bit
The IRQR acknowledge bit clears an IRQ interrupt request by
clearing the IRQ latch. If the IRQ latch is set again while in the IRQ
service routine (before an RTI instruction is executed), the CPU
re-enters the IRQ interrupt service routine unless the IRQ latch is
cleared. Writing a logic 1 to the IRQR acknowledge bit clears the IRQ
latch. Writing a logic 0 to the IRQR acknowledge bit has no effect on
the IRQ latch. The IRQR acknowledge bit always reads as a logic 0.
Address:
$000A
Bit 7
654321
Bit 0
Read:
IRQE
0
IRQF
0
Write:
R
IRQR
Reset:
10000000
= Unimplemented
R
= Reserved
Figure 4-4. IRQ Status/Control Register (ISCR)
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