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| 型號(hào)： | MC68HC05K3P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 114/132頁(yè) |
| 文件大小： | 2612K |
| 代理商： | MC68HC05K3P |
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Technical Data
MC68HC05K3 — Rev. 5
Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
9.3.2 PEEPROM Status/Control Register
The PEEPROM status/control register (PESCR) is located at $000F and
contains five user bits, as shown in Figure 9-3. Bit 1 is unimplemented
and always reads as a logic 0. The states of all bits except PEPCZF and
PEDATA are cleared by reset. The PEPCZF is set by reset; and the state
of the PEDATA bit following reset is dependent on the stored data in
bit 0 of the PEEPROM array.
PEPCZF — PEEPROM Column Zero Flag Bit
The PEPCZF is a flag bit that is set to a logical 1 when the first column
(COL0) of the EEPROM array is selected. If any other column is
selected, the PEPCZF flag bit is cleared. This flag bit can be used to
reduce the software code required to access one byte of the
PEEPROM. The PEPCZF is set following a reset, since the first
column is selected by the reset of the PEBSR. The software code
given in Table 9-1 is suggested for reading one byte from the
PEEPROM.
Address:
$000F
Bit 7
6
5
4321
Bit 0
Read: PEDATA
PEBULK
PEPGM
(DATA IN)
PEBYTE
CPEN
CPCLK
0
PEPCZF
Write:
Reset:
10
0
00001
= Unimplemented
Figure 9-3. PEEPROM Status/Control Register (PESCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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