參數(shù)資料
型號: MC68HC05K3P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 121/132頁
文件大?。?/td> 2612K
代理商: MC68HC05K3P
Personality EEPROM (PEEPROM)
PEEPROM Serial Programming
MC68HC05K3 — Rev. 5
Technical Data
Personality EEPROM (PEEPROM)
to the RESET pin. This device may be capable of heavily loading the
VDD supply source.
9.6.3 PEEPROM Serial Programming Mode Entry
The sequence for entry into the personality EEPROM serial
programming mode to program, erase, or read data is:
1. Connect all parallel device modules.
2. Apply 0 Vdc to the DATA, RESET, and SEL/CLK signal lines.
3. Apply a voltage VDDS to the VDD suppy line.
4. Apply VSELCKH to the SEL/CLK signal line.
5. Wait for the initial startup delay (16 or 4064 internal PH2 processor
clock cycles, depending on mask option). Then raise the RESET
signal line to VDDS.
6. Do not raise the DATA signal line to VDDS until after a time, tRDH.
7. During the select sequence, the SEL/CLK signal is toggled
between 0 Vdc and VSELCKH. The duration between transitions is
specified by tCLKHI and tCLKLO.
The device is now monitoring the IRQ and PB0 pins to determine the
type of procedure to execute. The state of the PB0 pin is examined
following each high-to-low transition of the IRQ pin, as shown in
The state of the PB0 pin during the second and third falling edges of
SEL/CLK determines the type of operation. If the operation is to program
or verify the contents of the personality EEPROM, an additional 128
falling edges are required to store or retrieve data. The type of internal
operation to be executed is defined in Table 9-2. The state of PB0 on the
first falling edge of SEL/CLK is of no consequence; however, PB0 must
remain low for a minimum of 10 internal clock cycles, tRDH, following
negation of RESET.
The time delays required for various PEEPROM serial program mode
operations are given in Table 9-3.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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