參數(shù)資料
型號(hào): MC68HC05K3P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 127/132頁
文件大小: 2612K
代理商: MC68HC05K3P
Technical Data
MC68HC05K3 — Rev. 5
Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
Table 9-3. Internal Test Time Delays
Symbol
Description
Min
Max
Time
VDDS
Serial mode VDD voltage
2.7
5.5
V
VSELCKH
SEL/CLK high voltage
1.5 x VDD
2.0 x VDD
V
tRDH
RESET rising edge to 1st rising edge of data
10
fOP cycles
tCLKHI
SEL/CLK active high time
32
fOP cycles
tCLKLO
SEL/CLK active low time (non-programming/erasing)
32
See Note
fOP cycles
tRSU
Read data in setup before falling edge of SEL/CLK
0
fOP cycles
tRHD
Read data in hold after falling edge of SEL/CLK
16
fOP cycles
tEPGM
Programming time for EEPROM cell
10
15
ms
tRCLK
RESET rising edge to falling edge of SEL/CLK
5
fOP cycles
tDRV
Data output drive after rising edge of SEL/CLK
4
8
fOP cycles
tHIZ
Data output hi-Z after rising edge of SEL/CLK
8
fOP cycles
tPBZ
Data hi-Z before rising edge of SEL/CLK
0
fOP cycles
tERBK
Bulk erase time for EEPROM array
30
ms
Note:
If computer operating properly (COP) watchdog timer is enabled through mask option, the maximum allowable
interval between any two successive high-to-low transitions of SEL/CLK is 7 x 217 fOP cycles.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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