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參數(shù)資料
| 型號(hào)： | MC68HC05P18ADWE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 108/130頁(yè) |
| 文件大?。?/td> | 1310K |
| 代理商： | MC68HC05P18ADWE |
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Serial Input/Output Ports (SIOP)
SIOP Signal Format
MC68HC05P18A
Technical Data
Serial Input/Output Ports (SIOP)
NON-DISCLOSURE
AGREEMENT
REQUIRED
Figure 9-2. SIOP Timing Diagram
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is mask option selectable. Available rates are OSC
divided by 2, 4, 8, or 16.
NOTE:
OSC divided by 2 is four times faster than the standard rate available on
the 68HC05P6.
Refer to 1.4 Mask Options for a description of available mask options.
9.3.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 ns before the rising edge
of SCK and remain valid for 100 ns after the rising edge of SCK. See
9.3.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. A mask option is included to allow the data to
SCK
SDO
SDI
100 ns
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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