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參數(shù)資料
| 型號： | MC68HC05P18ADWE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 62/130頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | MC68HC05P18ADWE |
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Central Processor Unit (CPU)
CPU Registers
MC68HC05P18A
Technical Data
Central Processor Unit (CPU)
NON-DISCLOSURE
AGREEMENT
REQUIRED
3.3.5 Condition Code Register
The condition code register (CCR) is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed. The following paragraphs describe the
functions of the condition code register.
Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The half-
carry flag is required for binary coded decimal (BCD) arithmetic
operations.
Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.
Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
Bit 7
654321
Bit 0
Read:
1
HIN
Z
C
Write:
Reset:
1
1U1U
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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