參數(shù)資料
型號: MC68HC05P4ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 54/102頁
文件大?。?/td> 930K
代理商: MC68HC05P4ADWR2
Simple Serial Input/Output Port (SIOP)
SIOP Registers
MC68HC05P4A — Rev. 6.0
Advance Information
MOTOROLA
Simple Serial Input/Output Port (SIOP)
55
bit and configures the SIOP for slave operation. MSTR may be set at
any time regardless of the state of SPE. Clearing MSTR will abort
any transmission in progress.
7.4.2 SIOP Status Register
This register is located at address $000B and contains only two bits.
SPIF — Serial Peripheral Interface Flag Bit
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. It has no effect on any
further transmissions and can be ignored without problem. SPIF is
cleared by reading the SSR with SPIF set followed by a read or write
of the serial data register. If it is cleared before the last edge of the
next byte, it will be set again. Reset clears this bit.
DCOL — Data Collision Bit
This is a read-only status bit which indicates that an invalid access to
the data register has been made. This can occur any time after the
first falling edge of SCK and before SPIF is set. A read or write of the
data register during this time will result in invalid data being
transmitted or received.
NOTE:
DCOL is cleared by reading the status register with SPIF set followed by
a read or write of the data register. If the last part of the clearing
sequence is done after another transmission has been started, DCOL
will be set again. If the DCOL bit is set and the SPIF is not set, clearing
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00000000
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
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