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參數(shù)資料
| 型號： | MC68HC05P4ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 58/102頁 |
| 文件大小： | 930K |
| 代理商： | MC68HC05P4ADWR2 |
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Timer
Counter
MC68HC05P4A — Rev. 6.0
Advance Information
MOTOROLA
Timer
59
8.3 Counter
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $18–$19 (counter register) or $1A–$1B (counter alternate
register). A read from only the least significant byte (LSB) of the
free-running counter ($19, $1B) receives the count value at the time of
the read. If a read of the free-running counter or counter alternate
register first addresses the most significant byte (MSB) ($18, $1A), the
LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed
after the first MSB read, even if the user reads the MSB several times.
This buffer is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1B) and, thus, completes a read
sequence of the total counter value. In reading either the free-running
counter or counter alternate register, if the MSB is read, the LSB also
must be read to complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is
always a read-only register. During a power-on reset, the counter is also
preset to $FFFC and begins running after the oscillator startup delay.
Because the free-running counter is 16 bits preceded by a fixed
divided-by-four prescaler, the value in the free-running counter repeats
every 262,144 internal bus clock cycles. When the counter rolls over
from $FFFF to $0000, the TOF bit is set. An interrupt can also be
enabled when counter rollover occurs by setting its interrupt enable bit
(TOIE).
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| MC68HC05P4CDWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P4P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P4P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P4DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05P4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P4P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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