參數(shù)資料
型號(hào): MC68HC05P4ADWR2
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 82/102頁(yè)
文件大?。?/td> 930K
代理商: MC68HC05P4ADWR2
Advance Information
MC68HC05P4A — Rev. 6.0
80
Instruction Set
MOTOROLA
Instruction Set
COM opr
COMA
COMX
COM opr,X
COM ,X
Complement Byte
(One’s Complement)
M
← ( ) = $FF – (M)
A
← ( ) = $FF – (M)
X
← ( ) = $FF – (M)
M
← ( ) = $FF – (M)
M
← ( ) = $FF – (M)
——
1
DIR
INH
IX1
IX
33
43
53
63
73
dd
ff
5
3
6
5
CPX #opr
CPX opr
CPX opr,X
CPX ,X
Compare Index
Register with
Memory Byte
(X) – (M)
— —
1
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
Decrement Byte
M
← (M) – 1
A
← (A) – 1
X
← (X) – 1
M
← (M) – 1
M
← (M) – 1
—— —
DIR
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
3
6
5
EOR #opr
EOR opr
EOR opr,X
EOR ,X
EXCLUSIVE OR
Accumulator with
Memory Byte
A
← (A) ⊕ (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
INC opr
INCA
INCX
INC opr,X
INC ,X
Increment Byte
M
← (M) + 1
A
← (A) + 1
X
← (X) + 1
M
← (M) + 1
M
← (M) + 1
—— —
DIR
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
6
5
JMP opr
JMP opr,X
JMP ,X
Unconditional Jump
PC
← Jump Address
—————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR opr
JSR opr,X
JSR ,X
Jump to Subroutine
PC
← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP
← (SP) – 1
Push (PCH); SP
← (SP) – 1
PC
← Conditional Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA #opr
LDA opr
LDA opr,X
LDA ,X
Load Accumulator with
Memory Byte
A
← (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 11-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
M
A
X
M
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC05P4DW 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT
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