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參數(shù)資料
| 型號： | MC68HC05P4ADWR3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 18/102頁 |
| 文件大?。?/td> | 930K |
| 代理商： | MC68HC05P4ADWR3 |
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Advance Information
MC68HC05P4A — Rev. 6.0
22
General Description
MOTOROLA
General Description
1.7.9 PD5 and TCAP/PD7
Port D is a 2-bit port. PD5 is I/O and TCAP/PD7 is input-only shared with
the timer input capture. The address of the port D data register is $0003,
and the data direction register is at address $0007. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. The TCAP/PD7 pin controls the
input capture feature for the on-chip programmable timer. This pin can
be read at any time even if the TCAP function is enabled.
1.8 Input/Output Programming
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin. For further information, see Table 1-1 and Figure 1-4.
Table 1-1. I/O Pin Functions
R/W(1)
1. R/W is an internal signal.
DDR
I/O Pin Function
00
The I/O pin is in input mode. Data is written into the
output data latch.
01
Data is written into the output data latch and output
to the I/O pin.
1
0
The state of the I/O pin is read.
11
The I/O pin is in an output mode. The output data
latch is read.
Note:
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| MC68HC05P4ADWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
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| MC68HC05P4CDWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05P4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P4P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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