參數(shù)資料
型號: MC68HC05P4ADWR3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 66/102頁
文件大?。?/td> 930K
代理商: MC68HC05P4ADWR3
Advance Information
MC68HC05P4A — Rev. 6.0
66
Computer Operating Properly (COP)
MOTOROLA
Computer Operating Properly (COP)
9.4 COP During Wait or Halt Mode
The COP will continue to operate normally during wait or halt mode. The
software should pull the device out of wait or halt mode periodically and
reset the COP by writing a logic 0 to the COPR bit to prevent a COP
reset.
9.5 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an IRQ is used
to exit stop mode, the COP counter will not be reset after the 4064-cycle
delay and will have that many cycles already counted when control is
returned to the program.
NOTE:
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.
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