參數(shù)資料
型號(hào)： MC68HC05PL4CSD
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 41/98頁(yè)
文件大小： 1019K
代理商： MC68HC05PL4CSD
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05PL4
7-2
REV 2.0
Table 7-1. I/O Pin Functions
7.1.1 Port Data Registers
Each port I/O pin has a corresponding bit in the Port Data Register. When a port
I/O pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin.
When a port pin is programmed as an input, any read of the Port Data Register
will return the logic state of the corresponding I/O pin. The locations of the Data
Registers for Port A, B, and C are at $0000, $0001 and $0002. The Port Data
Registers are unaffected by reset.
7.1.2 Port Data Direction Registers
Each port I/O pin may be programmed as an input by clearing the corresponding
bit in the DDR, or programmed as an output by setting the corresponding bit in the
DDR. The DDR for Port A, B, and C are located at $0005, $0006 and $0007. The
DDRs are cleared by reset.
NOTE
A “glitch” can be generated on an I/O pin when changing it from an input to an
output unless the data register is rst preconditioned to the desired state before
changing the corresponding DDR bit from a zero to a one.
7.2
PORT A
Port A is an 7-bit bidirectional port, with pins shared with other modules. The
Port A Data Register is at address $0000 and the Data Direction Register is at
address $0005. Port pins PA5 and PA6 are high current sink pins; see Electrical
Specications section for values.
Pin PA0 is only available on MC68HC05PL4. OSC2 replaces PA0 on
MC68HC05PL4B.
Pin PA1 becomes the DTMF output from the DAC when the DACEN bit is set in
the DAC Control and Data Register ($000F).
Pins PA2 and PA3 become the 16-bit timer TCAP and TCMP respectively, when
TCAPEN and TCMPEN are set in the Miscellaneous Control/Status Register
($001C).
R/W
DDR
I/O Pin Functions
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
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