- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45223 > MC68HC05PL4CSD (MOTOROLA INC) 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05PL4CSD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 50/98頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | MC68HC05PL4CSD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
16-BIT PROGRAMMABLE TIMER
MC68HC05PL4
9-4
REV 2.0
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF ag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains xed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a xed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF ag bit.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACRH
R ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
$001A
W
reset:
11111111
ACRL
R ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
$001B
W
reset:
11111100
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
ACRH ($001A)
TMR LSB
16-BIT COUNTER
÷ 4
INTERNAL
(XTAL
÷ 2)
RESET
CLOCK
ACRL ($001B)
INTERNAL
($FFFC)
DATA
READ
ACRH
READ
ACRL
READ
LATCH
BUS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705PL4BDW | 8-BIT, OTPROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705PL4BCDW | 8-BIT, OTPROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705PL4DW | 8-BIT, OTPROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05PL4BCSD | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05PL4P | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05PV8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05PV8A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05RC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。