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參數(shù)資料
| 型號： | MC68HC05RC17DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 117/128頁 |
| 文件大?。?/td> | 4788K |
| 代理商： | MC68HC05RC17DW |
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Phase-Locked Loop (PLL) Synthesizer
Phase-Locked Loop Control Register
MC68HC05RC17 — Rev. 2.0
General Release Specification
Phase-Locked Loop (PLL) Synthesizer
NON-DISCLOSURE
AGREEMENT
REQUIRED
10.3 Phase-Locked Loop Control Register
This read/write register contains the control bits that select the PLL
frequency and enable/disable the synthesizer.
BCS — Bus Clock Select
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1÷2). Once BCS has been changed, it may take up
to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of tPLLS after PLLON is set.
This bit should not be set unless the PLLON bit is already set on a
previous instruction. Reset clears this bit.
BWC — Bandwidth Control
This bit selects high bandwidth control when set and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
When the PLL is turned on, the BWC bit should be set to 1 for a time
90% tPLLS to allow the PLL time to acquire a frequency close to the
desired frequency. The BWC bit should then be cleared and software
should delay for a time, 10% tPLLS, to allow the PLL time to make the
final adjustments. The PLL clock cannot be used (BCS bit set).
Although it is NOT prohibited in hardware, the BCS bit should not be
set unless the BWC bit is cleared and the proper delay times have
been followed. The PLL will generate a lower jitter clock when the
BWC bit is cleared. Reset clears this bit.
Address:
$0007
Bit 7
654321
Bit 0
Read:
0
BCS
0
BWC
PLLON
VCOTST
PS1
PS0
Write:
Reset:
00001101
Figure 10-2. Phase-Locked Loop Control Register (PLLCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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