參數(shù)資料
型號: MC68HC05RC17DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 9/128頁
文件大?。?/td> 4788K
代理商: MC68HC05RC17DW
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set
General Release Specification
MC68HC05RC17 Rev. 2.0
Instruction Set
CLR
opr
CLRA
CLRX
CLR
opr,X
CLR ,X
Clear Byte
M ← $00
A ← $00
X ← $00
M ← $00
—— 0 1 —
DIR
INH
IX1
IX
3F
4F
5F
6F
7F
dd
ff
5
3
6
5
CMP #
opr
CMP
opr
CMP
opr
CMP
opr,X
CMP
opr,X
CMP ,X
Compare Accumulator with Memory Byte
(A) – (M)
— — ¤ ¤¤
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
COM
opr
COMA
COMX
COM
opr,X
COM ,X
Complement Byte (One’s Complement)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
—— ¤ ¤ 1
DIR
INH
IX1
IX
33
43
53
63
73
dd
ff
5
3
6
5
CPX #
opr
CPX
opr
CPX
opr
CPX
opr,X
CPX
opr,X
CPX ,X
Compare Index Register with Memory Byte
(X) – (M)
— — ¤ ¤ ¤
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
DEC
opr
DECA
DECX
DEC
opr,X
DEC ,X
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
—— ¤ ¤ —
DIR
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
3
6
5
EOR #
opr
EOR
opr
EOR
opr
EOR
opr,X
EOR
opr,X
EOR ,X
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) ⊕ (M)
— — ¤ ¤ —
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
INC
opr
INCA
INCX
INC
opr,X
INC ,X
Increment Byte
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
—— ¤ ¤ —
DIR
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
6
5
JMP
opr
JMP
opr
JMP
opr,X
JMP
opr,X
JMP ,X
Unconditional Jump
PC ← Jump Address
—————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
Table 11-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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