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參數(shù)資料
| 型號： | MC68HC05RC17DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 87/128頁 |
| 文件大?。?/td> | 4788K |
| 代理商： | MC68HC05RC17DW |
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Parallel Input/Output (I/O)
Port C
MC68HC05RC17 — Rev. 2.0
General Release Specification
Parallel Input/Output (I/O)
NON-DISCLOSURE
AGREEMENT
REQUIRED
7.5 Port C
Port C is a 6-bit bidirectional port (PC0–PC1 and PC4–PC7) which does
not share any of its pins with other subsystems. The port C data register
is at $0002 and the data direction register (DDR) is at $0006. Reset does
not affect the data register, but clears the data direction register, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. Port C pins PC4 through PC7 are
available only in higher pin count (>28 pin) packages.
NOTE:
Only two bits of port C are bonded out in 28-pin packages for the
MC68HC05RC17, although port C is truly a 6-bit port. Since pins
PC4–PC7 are unbonded, software should include the code to set their
respective data direction register locations to outputs to avoid floating
inputs.
7.6 Input/Output (I/O) Programming
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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