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參數(shù)資料
| 型號(hào)： | MC68HC05V7FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 126/170頁(yè) |
| 文件大?。?/td> | 589K |
| 代理商： | MC68HC05V7FN |
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SECTION 7: POWER SUPPLY AND REGULATION
MOTOROLA
Page 45
MC68HC05V7 Specification Rev. 1.0
SECTION 7
POWER SUPPLY AND REGULATION
The MC68HC05V7 contains a low-power CMOS on-chip fixed voltage regulator to provide
internal power to the MCU from an external DC source. The MCU features separate analog
and digital power and ground pins to help decrease common-mode noise contamination of
the analog subsystems. The supply pins are also grouped in adjacent pairs to permit
optimal decoupling and to minimize radiated RF emissions.
7.1
INTERNAL POWER SUPPLY
The on-chip voltage regulation and power supply control circuitry is comprised of four
elements: the primary regulator, the secondary regulator, the power mode control, and the
LVR circuitry. The primary internal regulator can be disabled through register control bits.
When it is desired to use an external voltage regulator, regulated power must be provided
to both sets of VDD/VSS pins. When the primary regulator is disabled, the regulator input
pin (VBATT) is still used to power the MDLC’s physical interface.
7.1.1
PRIMARY 5V REGULATOR
The primary 5V regulator accepts a regulated input supply and provides a regulated 5V
supply to all the digital sections of the device with the exception of the VIGN and power
supply control logic. The output of this regulator is also connected to the VDD pins to allow
for decoupling of the digital supply pins (VDD), to supply a decoupled and/or filtered supply
to the analog supply pin (VCCA) and to provide an external power source for off chip usage.
The regulator requires an external 10 uF capacitor for stability.
See Figure 7-6 :
MC68HC05V7 On-chip Power Supply Configuration for the most
suitable supply pin and external capacitor connections.
The primary regulator can be disabled through software by clearing the PDC bit of the
MISCELLANEOUS register (see Figure 7-1). Once disabled, the regulator can only be
enabled by a rising edge on the VIGN or BUS (if mask option enabled) pins. When disabled,
the primary regulator output will be connected to VSS if the VDDC mask option has been
selected. This prevents unintentional device operation using current sourced through
external pullup components.
Any loss of VBATT sufficient to trigger an LVR will cause the device to be reset. The device
will remain in the reset state for the duration of the LVR condition or until the internal VDD
drops below the functional level of the device, at which point reset no longer has meaning.
If the drop in VBATT that triggers an LVR is transient, the internal RST will be asserted for
a minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay).
7.1.2
SECONDARY REGULATOR
The secondary regulator provides an independent supply to the small amount of power
supply control logic required to provide some of the power moding functions. The
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