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參數(shù)資料
| 型號(hào)： | MC68HC05V7FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 33/170頁(yè) |
| 文件大?。?/td> | 589K |
| 代理商： | MC68HC05V7FN |
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MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 114
MC68HC05V7 Specification Rev. 1.0
15.5.2
J1850 FRAME FORMAT
All messages transmitted on the J1850 bus are structured using the format:
Each message has a maximum length of 12 bytes (excluding SOF, EOD, NB and EOF).
15.5.2.1
SOF - Start of Frame Symbol
All messages transmitted onto the J1850 bus must begin with an SOF symbol. This
indicates to any listeners on the J1850 bus the start of a new message transmission. The
SOF symbol is not used in the CRC calculation.
15.5.2.2
Data - In Message Data Bytes
The data bytes contained in the message include the message header bytes and any actual
data being transmitted to the receiving node. The MDLC can be used to transmit messages
using any of the three header formats outlined in the SAE J1850 document. However, the
MDLC does not utilize the IFR, Header type or functional/physical addressing bits defined
in the 1st byte of the 3-byte consolidated header message format. See
SAE J1850 - Class
B Data Communications Network Interface, for more information about 1- and 3-byte
headers.
Messages transmitted by the MDLC onto the J1850 bus must contain at least one data
byte, and therefore can be as short as one data byte and one CRC byte. Each data byte in
the message is 8 bits in length, transmitted MSB to LSB.
15.5.2.3
CRC - Cyclical Redundancy Check Byte
This byte is used by the receiver(s) of each message to determine if any errors have
occurred during the transmission of the message. The MDLC calculates the CRC byte and
appends it onto any messages transmitted onto the J1850 bus, and also performs CRC
detection on any messages it receives from the J1850 bus.
CRC generation uses the divisor polynomial X8+X4+X3+X2+1. The remainder polynomial
is initially set to all ones, and then each byte in the message after the SOF symbol is serially
processed through the CRC generation circuitry. The one’s complement of the remainder
then becomes the 8-bit CRC byte, which is appended to the message after the data bytes,
in MSB to LSB order.
When receiving a message, the MDLC uses the same divisor polynomial. All data bytes,
excluding the SOF and EOD symbols, but including the CRC byte, are used to check the
CRC. If the message is error free, the remainder polynomial will equal X7+X6+X2 ($C4),
regardless of the data contained in the message. If the calculated CRC does not equal $C4,
the MDLC will recognize this as a CRC error, and will discard the message, not informing
the CPU of the failure.
SOF
E
O
D
EOF
Datan
CRC
IFR
I
F
S
Idle
Figure 15-10:
J1850 Bus Message Format (VPW)
Optional
Data1
Data0
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