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參數(shù)資料
| 型號(hào)： | MC68HC05V7FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 145/170頁(yè) |
| 文件大?。?/td> | 589K |
| 代理商： | MC68HC05V7FNR2 |
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MOTOROLA
SECTION 9: PARALLEL I/O
Page 62
MC68HC05V7 Specification Rev. 1.0
read of the Port A/C Data Register will return the logic state of the corresponding I/O pin.
The Port A/C data register is unaffected by reset.
9.1.2
PORT A/C DATA DIRECTION REGISTER
Each Port A/C I/O pin may be programmed as an input by clearing the corresponding bit in
the DDRA/C, or programmed as an output by setting the corresponding bit in the DDRA/C.
The DDRA can be accessed at address $0004. The DDRC can be accessed at address
$0006. The DDRA and DDRC are cleared by reset.
9.1.3
PORT A/C I/O PIN INTERRUPTS
The inputs of all eight bits of Port A and Port C are ANDed into the IRQ input of the CPU.
Each port has its own interrupt request latch to enable the user to differentiate between the
IRQ sources. The port IRQ inputs are falling edge sensitive only. Any Port A or Port C pin
can be disabled as an interrupt input by setting the corresponding DDR bit. Any Port A or
Port C pins that are outputs will not cause a port interrupt when the pin transitions from a 1
to a 0. However, since all inputs pins are ANDed together to form the interrupt signal, any
input pin that remains low will inhibit the interrupt flag bit from being set when subsequent
pins transition low.
NOTE:
The BIH and BIL instructions will only apply to the level on the IRQ pin
itself, and not to the internal IRQ input to the CPU. Therefore BIH and BIL
cannot be used to obtain the result of the logical combination of the eight
pins of Port A or Port C.
9.2
PORT B
Port B is an 8-bit bidirectional port. Each Port B pin is controlled by the corresponding bits
in a data direction register and a data register as shown in Figure 9-2. PB6 and PB7 are
shared with 16 Bit Timer functions. See SECTION 11 16-BIT TIMER. The Port B Data
Register is located at address $0001. The Port B Data Direction Register (DDRB) is located
at address $0005. Reset clears the DDRB register. The Port B Data Register is unaffected
by reset
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