參數(shù)資料
型號： MC68HC05X4CDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝： PLASTIC, SOIC-28
文件頁數(shù)： 51/156頁
文件大小： 926K
代理商： MC68HC05X4CDW
Resets, Interrupts and Low Power Modes
Interrupts
MC68HC05X4 Rev 1.0
MOTOROLA
Resets, Interrupts and Low Power Modes
For More Information On This Product,
Go to: www.freescale.com
51
5-resets
Maskable
hardware
interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts
(internal and external) are masked. Clearing the I-bit allows interrupt
processing to occur.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I-bit is cleared.
MCAN interrupt
(CIRQ)
Several sources can trigger a CIRQ. The MCAN interrupt register at
$0023 is used to identify the source. Each CIRQ source can be
individually enabled (except the wake-up interrupt, which is always
enabled) by different bits of the MCAN control register at $0020.
The CIRQ sources are (see also
MCAN interrupt register (CINT)
):
Receive IRQ: this signals successful reception of a complete message,
Transmit IRQ: this signals successful transmission of a complete
message,
Error IRQ: this is set when either the error status or bus status bits in the
MCAN status register change state (see
MCAN status register
(CSTAT)
),
Data Overrun: an incoming message on the bus cannot be received
because both receive buffers are tied up,
Wake-up IRQ: this signals activity on the bus while the MCAN is in
SLEEP mode.
CIRQ interrupts are serviced by the routine located at the address
specified by the contents of $1FFA and $1FFB.
Wired-OR
interrupt (WOI)
An external WOI capability is provided on all I/O pins. When WOI is
enabled on a given pin (refer to
Input/output programming
and
Port
A
), an external interrupt is requested when this pin is pulled high. The
interrupt request is latched immediately following the rising edge of the
external WOI interrupt signal. It is then synchronised internally and
serviced by the interrupt routine whose start address is contained in
memory locations $1FF6 and $1FF7. The address of the latch bit for the
F
Freescale Semiconductor, Inc.
n
.
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