5.0-V DC Electrical Characteristics
MC68HC08GP32A MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
235
Input high voltage
All ports, IRQ, RST, OSC1
VIH
0.7
× VDD
—
VDD
V
Input low voltage
All ports, IRQ, RST, OSC1
VIL
VSS
—
0.2
× VDD
V
VDD supply current
Run(3)
Wait(4)
Stop(5)
25
°C
25
°C with TBM enabled(6)
25
°C with LVI and TBM enabled(6)
–40
°C to 85°C
–40
°C to 85°C with TBM enabled(6)
–40
°C to 85°C with LVI and TBM enabled(6)
IDD
—
15
4
2
20
300
—
50
500
20
8
—
35
—
mA
A
I/O ports Hi-Z leakage current(7)
IIL
–10
—
+10
A
Input current
IIn
–1
—
+1
A
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU
20
45
65
k
Capacitance
Ports (as input or output)
COut
CIn
—
12
8
pF
Monitor mode entry voltage
VTST
VDD + 2.5
—9.1
V
Low-voltage inhibit, trip falling voltage
VTRIPF
3.90
4.25
4.50
V
Low-voltage inhibit, trip rising voltage
VTRIPR
4.00
4.35
4.60
V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
VHYS
—100
—
mV
POR rearm voltage(8)
VPOR
0
—
100
mV
POR reset voltage(9)
VPORRST
0
700
800
mV
POR rise time ramp rate(10)
RPOR
0.035
—
V/ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit