參數(shù)資料
型號： MC68HC11A0CP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 114/158頁
文件大小： 3803K
代理商： MC68HC11A0CP2
SERIAL PERIPHERAL INTERFACE
MOTOROLA
TECHNICAL DATA
6-1
6
6 SERIAL PERIPHERAL INTERFACE
This section contains a description on the serial peripheral interface (SPI).
6.1 Overview and Features
The serial peripheral interface (SPI) is a synchronous interface which allows several
SPI microcontrollers or SPI-type peripherals to be interconnected. In a serial periph-
eral interface, separate wires (signals) are required for data and clock. In the SPI for-
mat, the clock is not included in the data stream and must be furnished as a separate
signal. The MC68HC11A8 SPI system may be configured either as a master or as a
slave. The SPI contains the following features:
Full Duplex, Three-Wire Synchronous Transfers
Master or Slave Operation
1.5 MHz (Maximum) Master Bit Frequency
3 MHz (Maximum) Slave Bit Frequency
Four Programmable Master Bit Rates
Programmable Clock Polarity and Phase
End-of-Transmission Interrupt Flag
Write Collision Flag Protection
Master-Master Mode Fault Protection
Easily Interfaces to Simple Expansion Parts (PLLs, D/As, Latches, Display Driv-
ers, etc.)
6.2 SPI Signal Descriptions
The four basic SPI signals (MISO, MOSI, SCK, and SS) are discussed in the following
paragraphs. Each signal is described for both the master and slave modes.
Any SPI output line has to have its corresponding data direction register bit set. If this
bit is clear, the line is disconnected from the SPI logic and becomes a general-purpose
input line. Any SPI input line is forced to act as an input regardless of what is in the
corresponding data direction register bit.
6.2.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an output in a slave
device. It is one of the two lines that transfer serial data in one direction, with the most
significant bit sent first. The MISO line of a slave device is placed in the high-imped-
ance state if the slave is not selected.
6.2.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an input in a slave
device. It is one of the two lines that transfer serial data in one direction with the most
significant bit sent first.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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