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| 型號： | MC68HC11A0CP2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 70/158頁 |
| 文件大小： | 3803K |
| 代理商： | MC68HC11A0CP2 |
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SIGNAL DESCRIPTIONS AND OPERATING MODES
MOTOROLA
TECHNICAL DATA
2-3
2
2.1.4 E Clock Output (E)
This is the output connection for the internally generated E clock which can be used
as a timing reference. The frequency of the E clock output is actually one fourth that
of the input frequency at the XTAL and EXTAL pins. When the E clock output is low
an internal process is taking place and, when high, data is being accessed. The E
clock signal is halted when the MCU is in STOP mode.
2.1.5 Interrupt Request (IRQ)
The IRQ input provides a means for requesting asynchronous interrupts to the
MC68HC11A8. It is program selectable (OPTION register) with a choice of either neg-
ative edge-sensitive or level-sensitive triggering, and is always configured to level-
sensitive triggering by reset. The IRQ pin requires an external pull-up resistor to VDD
(typically 4.7K ohm).
2.1.6 Non-Maskable Interrupt (XIRQ)
This input provides a means for requesting a non-maskable interrupt, after reset ini-
tialization. During reset, the X bit in the condition code register is set and any interrupt
is masked until MCU software enables it. The XIRQ input is level sensitive and re-
quires an external pull-up resistor to VDD.
2.1.7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/LIR,
MODB/VSTBY)
During reset, MODA and MODB are used to select one of the four operating modes.
Refer to Table 2-1. Paragraph 2.2 Operating Modes provides additional information.
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that an instruction is starting. All instructions are made up of a series of E
clock cycles. The LIR signal goes low during the first E clock cycle of each instruction
(opcode fetch). This output is provided as an aid in program debugging.
The VSTBY signal is used as the input for RAM standby power. When the voltage on
this pin is more than one MOS threshold (about 0.7 volts) above the VDD voltage, the
internal 256-byte RAM and part of the reset logic are powered from this signal rather
than the VDD input. This allows RAM contents to be retained without VDD power applied
to the MCU. Reset must be driven low before VDD is removed and must remain low
until VDD has been restored to a valid level.
Table 2-1 Operating Modes vs. MODA and MODB
MODB
MODA
Mode Selected
1
0
Single Chip
1
Expanded Multiplexed
0
Special Bootstrap
0
1
Special Test
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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