參數(shù)資料
型號: MC68HC11A1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 124/158頁
文件大?。?/td> 3803K
代理商: MC68HC11A1CFN3
ANALOG-TO-DIGITAL CONVERTER
MC68HC11A8
7-4
TECHNICAL DATA
7
CAUTION
When the multiple channel continuous scan mode is used, extra care
is needed in the design of circuitry driving the A/D inputs. Refer to the
A/D Pin Model and A/D Conversion Sequence figures in addition to
the following discussion. The charge on the capacitive DAC array pri-
or to the sample time is related to the voltage on the previously con-
verted channel. A charge share situation exists between the internal
DAC capacitance and the external circuit capacitance. Although the
amount of charge involved is small the rate at which it is repeated is
every 64 microseconds for an E clock of 2 MHz. The RC charging
rate of the external circuit must be balanced against this charge shar-
ing effect to avoid accuracy errors.
CD — Channel Select D
CC — Channel Select C
CB — Channel Select B
CA — Channel Select A
These four bits are used to select one of 16 A/D channels (see Table 7-1). When a
multiple channel mode is selected (MULT = 1), the two least-significant channel select
bits (CB and CA) have no meaning and the CD and CC bits specify which group of four
channels are to be converted. The channels selected by the four channel select control
bits are shown in Table 7-1.
*Not available in 48-pin package versions.
**This group of channels used during factory test.
Table 7-1 Analog-to-Digital Channel Assignments
Channel
Result in ADRx
CD
CC
CB
CA
Signal
if MULT=1
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4*
ADR1
0101
AN5*
ADR2
0110
AN6*
ADR3
0111
AN7*
ADR4
1000
Reserved
ADR1
1001
Reserved
ADR2
1010
Reserved
ADR3
1011
Reserved
ADR4
1100
VRH Pin**
ADR1
1101
VRL Pin**
ADR2
1110
(VRH)/2**
ADR3
1111
Reserved**
ADR4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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