參數(shù)資料
型號: MC68HC11A1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 92/158頁
文件大小: 3803K
代理商: MC68HC11A1CFN3
PARALLEL I/O
MOTOROLA
TECHNICAL DATA
4-1
4
4 PARALLEL I/O
The MC68HC11A8 has 40 I/O pins arranged as five 8-bit ports. All of these pins serve
multiple functions depending on the operating mode and data in the control registers.
This section explains the operation of these pins only when they are used for parallel
l/O.
Ports C and D are used as general purpose input and/or output pins under direct con-
trol of their respective data direction registers. Ports A, B, and E, with the exception of
port A pin 7, are fixed direction inputs or outputs and therefore do not have data direc-
tion registers. Port B, port C, the STRA pin, and the STRB pin are used for strobed
and/or handshake modes of parallel l/O, as well as general purpose l/O.
4.1 General-Purpose I/O (Ports C and D)
Each port l/O line has an associated bit in a specific port data register and port data
direction register. The data direction register bits are used to specify the primary direc-
tion of data for each l/O line. When an output line is read, the value at the input to the
pin driver is returned. When a line is configured as an input, that pin becomes a high-
impedance input. If a write is executed to an input line, the value does not affect the l/
O pin, but is stored in an internal latch. When the line becomes an output, this value
appears at the l/O pin. Data direction register bits are cleared by reset to configure l/
O pins as inputs.
The AS and R/W pins are dedicated to bus control while in the expanded multiplexed
operating modes, or parallel l/O strobes (STRA and STRB) while in the single chip op-
erating modes.
4.2 Fixed Direction I/O (Ports A, B, and E)
The lines for ports A, B, and E (except for port A bit 7) have fixed data directions. When
port A is being used for general purpose l/O, bits 0, 1, and 2 are configured as input
only and writes to these lines have no effect. Bits 3, 4, 5, and 6 of port A are configured
as output only and reads of these lines return the levels sensed at the input to the line
drivers. Port A bit 7 can be configured as either a general-purpose input or output us-
ing the DDRA7 bit in the pulse accumulator control register. When port B is being used
for general purpose output, it is configured as output only and reads of these lines will
return the levels sensed at the input of the pin drivers. Port E contains the eight A/D
channel inputs, but these lines may also be used as general purpose digital inputs.
Writes to the port E address have no effect.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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