參數(shù)資料
型號： MC68HC11D3CFN2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 87/138頁
文件大?。?/td> 1047K
代理商： MC68HC11D3CFN2
Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
52
Freescale Semiconductor
When an I bit related interrupt occurs, the I bit is automatically set by hardware after stacking the CCR
byte. The X bit is not affected. When an X bit related interrupt occurs, both the X and the I bit are
automatically set by hardware after stacking the CCR. A return-from-interrupt (RTI) instruction restores
the X and I bits to their preinterrupt request state.
4.3.5 Priority Structure
Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests. However one I bit
related interrupt source may be elevated to the highest I bit priority in the resolution circuit.
Six interrupt sources are not masked by the I bit in the CCR and have these fixed priority relationships:
1.
Reset
2.
Clock monitor failure
3.
COP failure
4.
Illegal opcode
5.
SWI
6.
XIRQ
SWI is actually an instruction and has highest priority, other than resets, in that once the SWI opcode is
fetched, no other interrupt can be honored until the SWI vector has been fetched.
Each of the previous sources is an input to the priority resolution circuit. The highest I bit masked priority
input to the resolution circuit is assigned to be connected to any one of the remaining I bit related interrupt
sources. This assignment is made under the software control of the HPRIO register. To avoid timing
races, the HPRIO register can be written only while the I bit related interrupts are inhibited (I bit of CCR
is logic 1). An interrupt that is assigned to this higher priority position is still subject to masking by any
associated control bits or by the I bit in the CCR. The interrupt vector address is not affected by assigning
a source to the higher priority position.
Figure 4-4, Figure 4-5, and Figure 4-6 illustrate the interrupt process as it relates to normal processing.
Figure 4-4 shows how the CPU begins from a reset, and how interrupt detection relates to normal opcode
fetches. Figure 4-5 is an expansion of a block in Figure 4-4 and shows how interrupt priority is resolved.
Figure 4-6 is an expansion of the SCI interrupt block of Figure 4-4 and shows the resolution of interrupt
sources within the SCI subsystem.
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