參數(shù)資料
型號: MC68HC11F1CFN2R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 32/163頁
文件大?。?/td> 711K
代理商: MC68HC11F1CFN2R2
MC68HC11F1
ANALOG-TO-DIGITAL CONVERTER
MOTOROLA
TECHNICAL DATA
10-3
Figure 10-2 Electrical Model of an A/D Input Pin (Sample Mode)
10.1.2 Analog Converter
Conversion of an analog input selected by the multiplexer occurs in this block. It con-
tains a digital-to-analog capacitor (DAC) array, a comparator, and a successive ap-
proximation register (SAR). Each conversion is a sequence of eight comparison
operations, beginning with the most significant bit (MSB). Each comparison deter-
mines the value of a bit in the successive approximation register.
The DAC array performs two functions. It acts as a sample and hold circuit during the
entire conversion sequence, and provides comparison voltage to the comparator dur-
ing each successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion
sequence is complete, the contents of the SAR are transferred to the appropriate re-
sult register.
A charge pump provides switching voltage to the gates of analog switches in the mul-
tiplexer. Charge pump output must stabilize between 7 and 8 volts, thus a delay of up
to 100
s must be imposed after setting ADPU before the converter can be used. The
charge pump is enabled by the ADPU bit in the OPTION register.
Power is provided to the A/D converter system through the AVDD and AVSS pins.
10.1.3 Digital Control
All A/D converter operations are controlled by bits in register ADCTL. In addition to se-
lecting the analog input to be converted, ADCTL bits indicate conversion status, and
control whether single or continuous conversions are performed. Finally, the ADCTL
bits determine whether conversions are performed on single or multiple channels.
10.1.4 Result Registers
Four 8-bit registers (ADR1–ADR4) store conversion results. Each of these registers
can be accessed by the processor in the CPU. The conversion complete flag (CCF)
DAC
CAPACITANCE
VRL
ANALOG
INPUT
PIN
~ 20 pF
+ ~ 20 V
~ 0.7 V
< 2 pF
INPUT
PROTECTION
DEVICE
400 nA
JUNCTION
LEAKAGE
DIFFUSION AND
POLY COUPLER
≤ 4 k
* This analog switch is closed only during the 12-cycle sample time.
*
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