參數(shù)資料
型號: MC68HC11F1CFN2R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 45/163頁
文件大?。?/td> 711K
代理商: MC68HC11F1CFN2R2
MC68HC11F1
ELECTRICAL CHARACTERISTICS
MOTOROLA
TECHNICAL DATA
A-5
NOTES:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
3. PWRSTL = 8 tcyc minimum on mask set C94R only.
Figure A-2 Timer Inputs
Table A-4 Control Timing
VDD = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
2.0 MHz
3.0 MHz
4.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation
fo
dc
2.0
dc
3.0
dc
4.0
MHz
E-Clock Period
tcyc
500
333
250
ns
Crystal Frequency
fXTAL
8.0
12.0
16.0
MHz
External Oscillator Frequency
4 fo
dc
8.0
dc
12.0
dc
16.0
MHz
Processor Control Setup Time
tPCSU = 1/4 tcyc + 50 ns
tPCSU
175
133
113
ns
Reset Input Pulse Width (Notes 2, 3)
(To Guarantee External Reset Vector)
(Minimum Input Time;
Can Be Preempted by Internal Reset)
PWRSTL
16
1
16
1
16
1
tcyc
Mode Programming Setup Time
tMPS
2—2—2—
tcyc
Mode Programming Hold Time
tMPH
10—10—10—
ns
Interrupt Pulse Width, IRQ Edge-Sensitive Mode
PWIRQ = tcyc + 20 ns
PWIRQ
520
353
270
ns
Wait Recovery Startup Time
tWRS
—4—4—4
tcyc
Timer Pulse Width, Input Capture Pulse Accumulator
Input
PWTIM = tcyc + 20 ns
PWTIM
520
353
270
ns
NOTES:
1. Rising edge sensitive input.
2. Falling edge sensitive input.
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7
2,3
PA7
1,3
PA[3:0]
2
PA[3:0]
1
PWTIM
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MC68HC11F1CFN5 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller