參數(shù)資料
型號: MC68HC11F1CFN3R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 3/174頁
文件大?。?/td> 981K
代理商: MC68HC11F1CFN3R2
MOTOROLA
SERIAL PERIPHERAL INTERFACE
MC68HC11F1
8-2
TECHNICAL DATA
Figure 8-1 SPI Block Diagram
8.2 SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received. A serial clock
line synchronizes shifting and sampling of the information on the two serial data lines.
A slave select line allows individual selection of a slave SPI device; slave devices that
are not selected do not interfere with SPI bus activities. On a master SPI device, the
select line can optionally be used to indicate a multiple master bus contention. Refer
INTERNAL
MCU CLOCK
DIVIDER
÷2
÷4 ÷16 ÷32
SELECT
SPI CLOCK (MASTER)
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK
LOGIC
S
M
S
PIN
CONTROL
LOGIC
MISO/
PD2
MOSI/
PD3
SCK/
PD4
SS/
PD5
M
S
MSTR
SPE
DWOM
SPR1
SPR0
MSTR
SPE
SPIE
SPE
DWOM
MSTR
CPHA
CPOL
SPR1
SPR0
SPCR SPI CONTROL REGISTER
SPIF
WCOL
MODF
SPSR SPI STATUS REGISTER
SPI CONTROL
INTERNAL
DATA BUS
SPI INTERRUPT
REQUEST
MSB
LSB
8
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