參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 157/174頁
文件大?。?/td> 981K
代理商： MC68HC11F1CFN3R2
MC68HC11F1
PARALLEL INPUT/OUTPUT
MOTOROLA
TECHNICAL DATA
6-3
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port C can only be configured for wired-OR operation when the MCU is in sin-
gle-chip or bootstrap modes.
DDC[7:0] — Data Direction for Port C
0 = Input
1 = Output
6.4 Port D
In all modes, port D bits [5:0] can be used either for general-purpose I/O, or with the
SCI and SPI subsystems. During reset, port D pins are configured as high impedance
inputs (DDRD bits cleared).
The DWOM control bit in the SPCR register disables port D’s P-channel output drivers.
Because the N-channel driver is not affected by DWOM, setting DWOM causes port
D to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTD bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port D bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation in any operating mode.
PORTC — Port C Data
$1006
Bit 7
654321
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
S. Chip or
Boot:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
IIIIIII
I
Expan. or
Test:
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DDRC — Data Direction Register for Port C
$1007
Bit 7
654321
Bit 0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
RESET:
0000000
0
PORTD — Port D Data
$1008
Bit 7
654321
Bit 0
—
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
0
IIIII
I
Alt. Pin
Func.:
—
SS
SCK
MOSI
MISO
TxD
RxD
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相關代理商/技術參數(shù)
參數(shù)描述
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