參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 8/174頁
文件大小： 981K
代理商： MC68HC11F1CFN3R2
MC68HC11F1
SERIAL PERIPHERAL INTERFACE
MOTOROLA
TECHNICAL DATA
8-7
8.5.2 Serial Peripheral Status
SPIF — SPI Interrupt Complete Flag
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR then access the SPDR. Unless SPSR is read
(with SPIF set) rst, attempts to write SPDR are inhibited.
WCOL — Write Collision
Clearing the WCOL bit is accomplished by reading the SPSR followed by an access of
0 = No write collision
1 = Write collision
Bit 5 — Not implemented
Always reads zero
MODF — Mode Fault
To clear the MODF bit, read the SPSR then write to the SPCR. Refer to 8.3.4 Slave
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not implemented
Always read zero
8.5.3 Serial Peripheral Data Register
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
SPSR — Serial Peripheral Status Register
$1029
Bit 7
654321
Bit 0
SPIF
WCOL
—
MODF
—
RESET:
0000000
0
SPDR — SPI Data Register
$102A
Bit 7
654321
Bit 0
Bit 7
654321
Bit 0
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相關代理商/技術參數(shù)
參數(shù)描述
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