參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 28/174頁
文件大?。?/td> 981K
代理商： MC68HC11F1CFN3R2
MC68HC11F1
TIMING SYSTEM
MOTOROLA
TECHNICAL DATA
9-17
Bit 7 — Not implemented
Always reads zero
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Bit 3 — Not implemented
Always reads zero
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 function enable (No IC4)
1 = Input capture 4 function enable (No OC5)
RTR[1:0] — RTI Interrupt Rate Selects
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The PACNT is readable even if PAI is not active in gat-
ed time accumulation mode. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
PACTL — Pulse Accumulator Control
$1026
Bit 7
654321
Bit 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
RESET:
0000000
0
Table 9-6 Pulse Accumulator Edge Detection Control
PAMOD
PEDGE
Action on Clock
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A zero on PAI inhibits counting.
1
A one on PAI inhibits counting.
PACNT — Pulse Accumulator Count
$1027
Bit 7
654321
Bit 0
Bit 7
654321
Bit 0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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