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參數(shù)資料
| 型號(hào)： | MC68HC11F1CFN4R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 81/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 1K RAM 4MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 30 |
| 程序存儲(chǔ)器類型： | ROMless |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC68HC11F1CFN4RCT |
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CENTRAL PROCESSING UNIT
TECHNICAL DATA
3-5
When an interrupt is recognized, the current instruction finishes normally, the return
address (the current value in the program counter) is pushed onto the stack, all of the
CPU registers are pushed onto the stack, and execution continues at the address
specified by the vector for the interrupt. At the end of the interrupt service routine, an
RTI instruction is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return address.
There are instructions that push and pull the A and B accumulators and the X and Y
index registers. These instructions are often used to preserve program context. For
example, pushing accumulator A onto the stack when entering a subroutine that uses
accumulator A, and then pulling accumulator A off the stack just before leaving the
subroutine, ensures that the contents of a register will be the same after returning from
the subroutine as it was before starting the subroutine.
3.1.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to
be executed. After reset, the program counter is initialized from one of six possible
vectors, depending on operating mode and the cause of reset.
3.1.6 Condition Code Register (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two inter-
rupt masking bits, (I and X) and a stop disable bit (S). In the M68HC11 CPU, condition
codes are automatically updated by most instructions. For example, load accumulator
A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the
N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY),
and transfer/exchange instructions do not affect the condition codes. Refer to Table
3-2, which shows what condition codes are affected by a particular instruction.
3.1.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an
arithmetic operation. The C bit also acts as an error flag for multiply and divide opera-
tions. Shift and rotate instructions operate with and through the carry bit to facilitate
multiple-word shift operations.
3.1.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V
bit is cleared.
Table 3-1 Reset Vector Comparison
POR or RESET Pin
Clock Monitor
COP Watchdog
Normal
$FFFE, F
$FFFC, D
$FFFA, B
Test or Boot
$BFFE, F
$BFFC, D
$BFFA, B
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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