參數(shù)資料
型號： MC68HC11F1MFN4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 103/163頁
文件大小： 711K
代理商： MC68HC11F1MFN4
MOTOROLA
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11F1
4-6
TECHNICAL DATA
4.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are pro-
tected against writes except under special circumstances. The following table lists reg-
isters that can be written only once after reset or that must be written within the first 64
cycles after reset.
$1028
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR
$1029
SPIF
WCOL
0
MODF
0
Bit 0
SPSR
$102A
Bit 7
654321
Bit 0
SPDR
$102B
TCLR
0
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
BAUD
$102C
R8
T8
0
M
WAKE
0
SCCR1
$102D
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCCR2
$102E
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
SCSR
$102F
Bit 7
654321
Bit 0
SCDR
$1030
CCF
0
SCAN
MULT
CD
CC
CB
CA
ADCTL
$1031
Bit 7
654321
Bit 0
ADR1
$1032
Bit 7
654321
Bit 0
ADR2
$1033
Bit 7
654321
Bit 0
ADR3
$1034
Bit 7
654321
Bit 0
ADR4
$1035
0
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
BPROT
$1036
Reserved
$1037
Reserved
$1038
GWOM
CWOM
CLK4X
00000
OPT2
$1039
ADPU
CSEL
IRQE
DLY
CME
FCME
CR1
CR0
OPTION
$103A
Bit 7
654321
Bit 0
COPRST
$103B
ODD
EVEN
0
BYTE
ROW
ERASE
EELAT
EEPGM
PPROG
$103C
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
HPRIO
$103D
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
INIT
$103E
TILOP
0
OCCR
CBYP
DISR
FCM
FCOP
0
TEST1
$103F
EE3`
EE2
EE1
EE0
1
NOCOP
1
EEON
CONFIG
$1040
Reserved
to
$105B
Reserved
$105C
IO1SA
IO1SB
IO2SA
IO2SB
GSTHA
GSTHB
PSTHA
PSTHB
CSSTRH
$105D
IO1EN
IO1PL
IO2EN
IO2PL
GCSPR
PCSEN
PSIZA
PSIZB
CSCTL
$105E
GA15
GA14
GA13
GA12
GA11
GA10
0
CSGADR
$105F
IO1AV
IO2AV
0
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC
CSGSIZ
Table 4-1 Register and Control Bit Assignments (Continued)
The register block can be remapped to any 4-Kbyte boundary.
Bit 7
654321
Bit 0
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