參數(shù)資料
型號(hào): MC68HC11F1MFN4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 38/163頁(yè)
文件大?。?/td> 711K
代理商: MC68HC11F1MFN4
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MOTOROLA
ANALOG-TO-DIGITAL CONVERTER
MC68HC11F1
10-8
TECHNICAL DATA
NOTE
When the multiple-channel continuous scan mode is used, extra care
is needed in the design of circuitry driving the A/D inputs. The charge
on the capacitive DAC array before the sample time is related to the
voltage on the previously converted channel. A charge share situa-
tion exists between the internal DAC capacitance and the external
circuit capacitance. Although the amount of charge involved is small,
the rate at which it is repeated is every 64
s for an E clock of 2 MHz.
The RC charging rate of the external circuit must be balanced against
this charge sharing effect to avoid errors in accuracy. Refer to
M68HC11 Reference Manual (M68HC11RM/AD) for further informa-
tion.
CD–CA — Channel Selects D–A
Refer to Table 10-2. When a multiple channel mode is selected (MULT = 1), the two
least significant channel select bits (CB and CA) have no meaning and the CD and CC
bits specify which group of four channels is to be converted.
*Used for factory testing
10.9 A/D Converter Result Registers
These read-only registers hold an 8-bit conversion result. Writes to these registers
have no effect. Data in the A/D converter result registers is valid when the CCF flag in
the ADCTL register is set, indicating a conversion sequence is complete. If conversion
results are needed sooner, refer to Figure 10-3, which shows the A/D conversion se-
quence diagram.
Table 10-2 A/D Converter Channel Selection
Channel Select
Control Bits
Channel Signal
Result in ADRx if
MULT = 1
CD:CC:CB:CA
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4
ADR1
0101
AN5
ADR2
0110
AN6
ADR3
0111
AN7
ADR4
1000
Reserved
1001
Reserved
1010
Reserved
1011
Reserved
1100
VRH*
ADR1
1101
VRL*
ADR2
1110
(VRH)/2*
ADR3
1111
Reserved*
ADR4
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