參數(shù)資料
型號: MC68HC11F1MFN4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 151/163頁
文件大?。?/td> 711K
代理商: MC68HC11F1MFN4
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC11F1
7-2
TECHNICAL DATA
Figure 7-1 SCI Transmitter Block Diagram
7.3 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register
receives data and transfers it to a parallel receive data register (SCDR) as a complete
word. This double buffered operation allows a character to be shifted in serially while
another character is already in the SCDR. An advanced data recovery scheme distin-
guishes valid data from noise in the serial data stream. The data input is selectively
sampled to detect receive data, and a majority voting circuit determines the value and
integrity of each bit.
FE
NF
OR
IDLE
RDRF
TC
TDRE
SCSR INTERRUPT STATUS
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
SCCR2 SCI CONTROL 2
TRANSMITTER
CONTROL LOGIC
TCIE
TC
TIE
TDRE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
PIN BUFFER
AND CONTROL
H (8) 76543210
L
10 (11) - BIT Tx SHIFT REGISTER
PD1/
TxD
SCDR Tx BUFFER
TRANSFER
Tx
BUFFER
SHIFT
ENABLE
JAM
ENABLE
PREAMBLE—JAM
1's
BREAK—JAM
0's
(WRITE-ONLY)
FORCE PIN
DIRECTION (OUT)
SIZE
8/9
WAKE
M
T8
R8
SCCR1 SCI CONTROL 1
TRANSMITTER
BAUD RATE
CLOCK
DDD1
8
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