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MC68HC11PH8
MOTOROLA
xi
LIST OF FIGURES
Figure
Number
Page
Number
Title
LIST OF FIGURES
1-1
MC68HC11PH8/
MC68HC711PH8 block diagram ..................................................1-3
2-1
84-pin PLCC/
CERQUAD pinout .............................................................................2-1
2-2
112-pin TQFP pinout ..............................................................................................2-2
2-3
External reset circuitry............................................................................................2-3
2-4
Oscillator connections (VDDSYN = 0, PLL disabled) .............................................2-4
2-5
Oscillator connections (VDDSYN = 1, PLL enabled)..............................................2-5
2-6
PLL circuit...............................................................................................................2-6
2-7
RAM stand-by connections.....................................................................................2-13
3-1
MC68HC11PH8/
MC68HC711PH8 memory map ...................................................3-3
3-2
Example of expanded mode FREEZ actions..........................................................3-13
3-3
RAM and register overlap .......................................................................................3-15
5-1
SCI baud rate generator circuit diagram.................................................................5-1
5-2
SCI1 block diagram ................................................................................................5-3
5-3
Interrupt source resolution within SCI.....................................................................5-14
6-1
MI BUS timing.........................................................................................................6-2
6-2
Biphase coding and error detection........................................................................6-3
6-3
MI BUS block diagram ............................................................................................6-5
6-4
A typical interface between the MC68HC11PH8 and the MI BUS..........................6-6
7-1
SPI block diagram...................................................................................................7-2
7-2
SPI transfer format..................................................................................................7-3
8-1
Timer clock divider chains (PLL enabled — VDDSYN high) ..................................8-5
8-2
Timer clock divider chains (PLL disabled — VDDSYN low) ...................................8-6
8-3
Capture/compare block diagram.............................................................................8-7
8-4
Pulse accumulator block diagram...........................................................................8-24
8-5
PWM timer block diagram.......................................................................................8-29
8-6
PWM duty cycle......................................................................................................8-34
8-7
8-bit modulus timer system.....................................................................................8-36
9-1
A/D converter block diagram ..................................................................................9-2
9-2
Electrical model of an A/D input pin (in sample mode)...........................................9-3
9-3
A/D conversion sequence.......................................................................................9-4
10-1
Processing ow out of reset (1 of 2) .....................................................................10-19
10-2
Processing ow out of reset (2 of 2) .....................................................................10-20
10-3
Interrupt priority resolution (1 of 3) .......................................................................10-21
TPG
17