MOTOROLA
8-2
FLASH EEPROM MODULE
MC68HC16R1/916R1
USER’S MANUAL
Four additional flash EEPROM words in the control block can contain bootstrap
information for use during reset. Control registers are located in supervisor data
space. Refer to
D.8 Flash EEPROM Modules
for register and bit field information.
The control register blocks for the 16- and 32-Kbyte flash EEPROM modules start at
locations $YFF800 and $YFF820, respectively. The following register descriptions ap-
ply to the corresponding register in either control block. References to FEExMCR, for
example, apply to both FEE1MCR (in the 16-Kbyte module) and FEE2MCR (in the 32-
Kbyte module.)
A number of control register bits have associated bits in “shadow” registers. The
values of the shadow bits determine the reset states of the control register bits. Shad-
ow registers are programmed or erased in the same manner as a location in the array,
using the address of the corresponding control registers.When a shadow register is
programmed, the data is not written to the corresponding control register. The new
data is not copied into the control register until the next reset. The contents of shadow
registers are erased when the array is erased.
Configuration information is specified and programmed independently of the array.
After reset, registers in the control block that contain writable bits can be modified.
Writes to these registers do not affect the associated shadow register. Certain
registers can be written only when LOCK = 0 or STOP = 1 in FEExMCR.
8.2 Flash EEPROM Array
The base address registers specify the starting address of the flash EEPROM array.
The user programs the reset base address. The base address of the 16-Kbyte array
must be on a 16-Kbyte boundary; the base address of the 32-Kbyte array must be on
a 32-Kbyte boundary. Behavior will be indeterminate if one flash EEPROM array over-
laps the other.
The base address must also be set so that an array does not overlap a flash EEPROM
control block in the data space memory map. If an array does overlap a control block,
accesses to the 32 bytes in the array that is overlapped are ignored, allowing the flash
EEPROM control blocks to remain accessible. If the array overlaps the control block
of another module, the results will be indeterminate.
8.3 Flash EEPROM Operation
The following paragraphs describe the operation of the flash EEPROM module during
reset, system boot, normal operation, and while it is being programmed or erased.
8.3.1 Reset Operation
Reset initializes all registers to certain default values. Some of these reset values are
programmable by the user and are contained in flash EEPROM shadow registers.
If the state of the STOP shadow bit is zero, and bus pin DATA14 is pulled high during
reset, the STOP bit in the FEExMCR is cleared during reset. The array responds
normally to the bootstrap address range and the flash EEPROM array base address.