MOTOROLA
9-2
BLOCK-ERASABLE FLASH EEPROM
MC68HC16R1/916R1
USER’S MANUAL
Configuration information is specified and programmed independently of the
BEFLASH array. After reset, registers in the control block that contain writable bits can
be modified. Writes to these registers do not affect the associated shadow register.
Certain registers are writable only when the LOCK bit in BFEMCR is disabled or when
the STOP bit in BFEMCR is set. These restrictions are noted in the individual register
descriptions.
9.3 BEFLASH Array
The base address registers specify the starting address of the BEFLASH array. A
default base address can be programmed into the base address shadow registers.
The array base address must be on a 2-Kbyte boundary. Because the states of
ADDR[23:20] follow the state of ADDR19, addresses in the range $080000 to
$F7FFFF cannot be accessed by the CPU16. If the BEFLASH array is mapped to
these addresses, the system must be reset before the array can be accessed.
Avoid using a base address value that causes the array to overlap control registers. If
a portion of the array overlaps the EEPROM register block, the registers remain
accessible, but accesses to that portion of the array are ignored. If the array overlaps
the control block of another module, however, those registers may become
inaccessible. If the BEFLASH array overlaps another memory array (RAM or flash
EEPROM), proper access to one or both arrays may not be possible.
9.4 BEFLASH Operation
The following paragraphs describe the operation of the BEFLASH during reset, sys-
tem boot, normal operation, and while it is being programmed or erased.
9.4.1 Reset Operation
Reset initializes all BEFLASH control registers. Some bits have fixed default values,
and some take values that are programmed into the associated BEFLASH shadow
registers.
If the state of the STOP shadow bit is zero, and data bus pin DATA15 is pulled high
during reset, the STOP bit in BFEMCR is cleared during reset, and the module
responds to accesses in the range specified by BFEBAH and BFEBAL. When the
BOOT bit is cleared, the module also responds to bootstrap vector accesses.
If the state of the STOP shadow bit is one, or data bus pin DATA15 is pulled low during
reset, the STOP bit in BFEMCR is set during reset and the BEFLASH array is disabled.
The module does not respond to array or bootstrap vector accesses until the STOP bit
is cleared. This allows an external device to respond to accesses to the BEFLASH
array address space or to bootstrap accesses. The erased state of the shadow bits is
one. An erased module comes out of reset in STOP mode.