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| 型號： | MC68HC2681P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 33/88頁 |
| 文件大?。?/td> | 726K |
| 代理商： | MC68HC2681P |
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Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-9
4
X—Not Used, may be set to either 0 or 1
Miscellaneous Commands (Bits 6, 5, 4)
0 0 0 = No Command
0 0 1 = Reset MR Pointer to MR1
0 1 0 = Reset Receiver
0 1 1 = Reset Transmitter
1 0 0 = Reset Error Status
1 0 1 = Reset Channel’s Break-Change Interrupt
1 1 0 = Start Break
1 1 1 = Stop Break
Transmitter Commands (Bits 3 and 2)
0 0 = No Action, Stays in Present Mode
0 1 = Transmitter Enabled
1 0 = Transmitter Disabled
1 1 = Don’t Use, Indeterminate
Receiver Commands (Bits 1 and 0)
0 0 = No Action, Stays in Present Mode
0 1 = Receiver Enabled
1 0 = Receiver Disabled
1 1 = Don’t Use, Indeterminate
These status bits are appended to the corresponding data character in the receive FIFO and are valid only when the RxRDY bit
is set. A read of the status register provides these bits (seven through five) from the top of the FIFO together with bits four through
zero. These bits are cleared by a reset error status command. In character mode, they are discarded when the corresponding
data character is read from the FIFO.
All Bits
0 = No
1 = Yes
Channel A/B Status Register (SRA/SRB)
7*
6*
5*
43210
RECEIVED
BREAK
FRAMING
ERROR
PARITY
ERROR
OVERRUN
ERROR
TXEMT
TXRDY
FFULL
RXRDY
Output Port Configuration Register (OPCR)
76543210
OP7
OP6
OP5
OP4
OP3
OP2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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