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| 型號(hào)： | MC68HC2681P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 44/88頁 |
| 文件大?。?/td> | 726K |
| 代理商： | MC68HC2681P |
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Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-19
4
4.3.8 Channel B Command Register (CRB)
The bit definitions for this register are identical to those for CRA, except that all control
actions apply to the channel B receiver and transmitter and their corresponding inputs and
outputs.
4.3.9 Channel A Status Register (SRA)
4.3.9.1 CHANNEL A RECEIVED BREAK - SRA[7]. This bit indicates an all-zero
character of the programmed length has been received without a stop bit. This bit is valid
only when the RxRDY bit is set (SRA[0] = 1). Only a single FIFO position is occupied when
a break is received; additional entries to the FIFO are inhibited until the channel A receiver
serial data input line returns to the marking state.
The break-detect circuitry can detect a break that starts in the middle of a received
character; however, the break condition must persist completely through the end of the
current character and the next character time to be recognized. (The MC68681
incorrectly signalled a break if the data bits and stop bit were 0, but the parity bit was 1.
This is not true in the MC68HC681.)
4.3.9.2 CHANNEL A FRAMING ERROR - SRA[6]. This bit (when set) indicates that a
stop bit was not detected when the corresponding data character in the FIFO was
received. The stop bit check is made in the middle of the first stop bit position. This bit is
valid only when the RxRDY bit is set (SRA[0] = 1). Framing error and break are exclusive:
At least one data bit and/or the parity bit must have been a 1 to signal a framing error.
After a framing error, the receiver does not wait for the line to return to the marking state
(high); if the line remains low for 1/2 a bit time after the stop bit sample (that is, the nominal
end of the first stop bit), the receiver treats it as the beginning of a new start bit.
4.3.9.3 CHANNEL A PARITY ERROR - SRA[5]. This bit becomes set when the "with
parity" or "force parity" mode is programmed by mode register one and the corresponding
character in the FIFO is received with incorrect parity. In the multidrop mode, the parity
error bit position stores the received address/data bit. This bit is valid only when the
RxRDY bit is set (SRA[0] = 1).
4.3.9.4 CHANNEL A OVERRUN ERROR - SRA[4]. This bit (when set) indicates one or
more characters in the received data stream have been lost. It becomes set on receipt of
a valid start bit when the FIFO is full and a character is already in the receive shift register
waiting for an empty FIFO position. When this occurs, the character in the receive shift
register (and its break detect, parity error, and framing error status, if any) is lost. A reset
error status command clears this bit.
4.3.9.5 CHANNEL A TRANSMITTER EMPTY - SRA[3]. This bit will be set when the
channel A transmitter underruns; i.e., both the transmit holding register and the transmit
shift register are empty. It is set after transmission of the last stop bit of a character if no
character is in the transmit holding register awaiting transmission. It is cleared when the
CPU loads the transmit holding register or when the transmitter is disabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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