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| 型號： | MC68HC2681P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 7/88頁 |
| 文件大?。?/td> | 726K |
| 代理商： | MC68HC2681P |
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Introduction
1-4
MC68HC681 USER’S MANUAL
MOTOROLA
1
1.1 INTERNAL CONTROL LOGIC
The internal control logic receives operation commands from the central processing unit
(CPU) and generates appropriate signals to the internal sections to control device operation.
The internal control logic allows access to the registers within the DUART and performs
various commands by decoding the four register-select lines (RS1 through RS4). Besides
the four register-select lines, there are three other inputs to the internal control logic from the
CPU: read/write (R/W), which allows read and write transfers between the CPU and DUART
via the data bus buffer; chip-select (CS), which is the DUART chip-select; and reset
(RESET), which initializes or resets the DUART. The data transfer acknowledge (DTACK)
signal, which is asserted during read, write, or interrupt-acknowledge cycles, is the internal
control logic output. The DTACK signal indicates to the CPU that data has been latched on
a CPU write cycle or that valid data is present on the data bus during a CPU read cycle or
interrupt-acknowledge (IACK) cycle.
1.2 TIMING LOGIC
The timing logic consists of a crystal oscillator, a baud-rate generator (BRG), a
programmable 16-bit counter/timer (C/T), and four clock selectors. The crystal oscillator
operates directly from a 3.6864 MHz crystal connected across the X1 and X2 inputs or from
an external clock of the appropriate frequency connected to X1. The X1 clock serves as the
basic timing reference for the baud-rate generator, the C/T, and other internal circuits. The
part can operate without an X1 clock but with the following restrictions:
The X1 input must be connected to GND or VCC
The receiver(s) and transmitter(s), if used, must not be programmed to select any of the
18 standard rates generated by the BRG
The counter/timer, if used, must not be programmed to the X1 or X1/16 selection
The change-detect on IP0-IP3 will not operate
DTACK will not be generated on any bus cycle
The baud-rate generator operates from the X1 clock input and can generate 18 commonly
used data communication baud rates ranging from 50 to 38.4k by producing internal clock
outputs at 16 times the actual baud rate. The C/T can produce a 16X clock for other baud
rates by counting down its programmed clock source. Other baud rates can also be derived
by connecting 16X or 1X clocks to certain input port pins that have alternate functions as
receiver or transmitter clock inputs. Four clock selectors allow the independent selection of
any of these baud rates for each receiver and transmitter. Customers can program the 16-
bit C/T within the DUART to use one of several clock sources as its input. The output of the
C/T is available to the internal clock selectors and can also be programmed to appear at
parallel output OP3. In the timer mode, the C/T acts as a programmable divider and can
generate a square-wave output at OP3. In the counter mode, the C/T can be started and
stopped under program control. When stopped, the CPU can read its contents. The counter
counts down the number of pulses stored in the concatenation of the C/T upper register and
C/T lower register and produces an interrupt. This is a system-oriented feature that can be
used to record timeouts when implementing various application protocols.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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