參數(shù)資料
型號: MC68HC705E6VDWR3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 122/140頁
文件大小: 1141K
代理商: MC68HC705E6VDWR3
Resets and Interrupts
MC68HC05E6 — Rev. 1.0
82
Resets and Interrupts
MOTOROLA
LVIRST — LVI interrupt reset
This bit is write-only; any read will always return zero. Writing a ‘1’ to
this bit resets the LVI interrupt routine.
LVIE — LVI interrupt enable
1 = LVI interrupts enabled; an interrupt will be generated on each
high to low transition and each low to high transition of the LVI
pin (but not the first low to high transition during, or after a
power-on reset).
0 = LVI interrupts disabled; a high to low transition on the LVI pin
will be handled by the user software.
NOTE:
The bits which are shown shaded in the LVI/options register are
described in Mask options.
16-bit timer
interrupts
There are three different timer interrupt flags (ICF, OCF and TOF) that
will cause a timer interrupt whenever they are set and enabled. These
three interrupt flags are found in the three most significant bits of the
timer status register (TSR) at location $13. ICF, OCF and TOF will vector
to the service routine defined by $1FF4 - $1FF5 as shown in Table 11.
There are three corresponding enable bits (ICIE, OCIE and TOIE) which
are located in the timer control register (TCR) at address $12. Full details
of the programmable timer can be found in Programmable Timer.
Keyboard interrupt
When configured as input pins, port C bits 0–7 provide a wired-OR
keyboard interrupt facility and will generate an interrupt provided the
keyboard interrupt enable bit (KIE) in the keyboard/timer register
(KEY/TIM) is set.When configured as inputs with keyboard interrupt
capability, the pins can also have pull-ups connected to them by
correctly configuring the DDRC and CONFC bits as outlined in Table 5.
The interrupt vector for this interrupt is located at $1FF2, $1FF3. Further
information on the keyboard interrupt facility can be found in Port C.
10-resets
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