參數(shù)資料
型號: MC68HC705E6VDWR3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 87/140頁
文件大?。?/td> 1141K
代理商: MC68HC705E6VDWR3
Core Timer
MC68HC05E6 — Rev. 1.0
50
Core Timer
MOTOROLA
Core timer counter
register (CTCR)
The core timer counter register is a read-only register, which contains
the current value of the 8-bit ripple counter at the beginning of the timer
chain. Reset clears this register.
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains
active. If the CTIMER interrupts are enabled, then a CTIMER interrupt
will cause the processor to exit the WAIT mode.
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an external reset, the internal oscillator will
restart, followed by an internal processor stabilization delay (t
PORL). The
timer is then cleared and operation resumes.
Table 8 Example RTI periods
Bus frequency
fOP = 500 kHz
Bus frequency
fOP = 1 MHz
Bus frequency
fOP = 2 MHz
RT1
RT0
Division
ratio
RTI
period
Minimum
COP
period
RTI
period
Minimum
COP
period
RTI
period
Minimum
COP
period
00
214
32.8ms
229.38ms
16.4ms
114.69ms
8.2ms
57.34ms
01
215
65.5ms
458.75ms
32.8ms
229.38ms
16.4ms
114.69ms
10
216
131.1ms
917.5ms
65.5ms
458.75ms
32.8ms
229.38ms
11
217
262.1ms
1.835s
131.1ms
917.50ms
65.5ms
458.75ms
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer counter (CTCR)
$0009
0000 0000
6-ctimer
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相關代理商/技術參數(shù)
參數(shù)描述
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