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| 型號： | MC68HC705J2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | member of the low-cost |
| 中文描述： | 成員低成本 |
| 文件頁數(shù)： | 34/82頁 |
| 文件大?。?/td> | 583K |
| 代理商： | MC68HC705J2 |
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RESETS AND INTERRUPTS
5-4
Rev. 2
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The return from interrupt (RTI) instruction causes the CPU to recover the CPU
registers from the stack as shown in
Figure 5-2
.
5.2.1 Timer Interrupts
The timer generates two kinds of interrupts:
Timer overflow interrupt
Real-time interrupt
Setting the interrupt mask in the condition code register disables timer interrupts.
5.2.1.1 Timer Overflow Interrupts
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while
the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the
timer control and status register. See
7.2 Timer Control and Status Register
(TCSR)
.
5.2.1.2 Real-Time Interrupts
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while
the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer
control and status register. See
7.2 Timer Control and Status Register (TCSR)
.
5.2.2 External Interrupt
When a falling edge occurs on theIRQ pin, an external interrupt request is latched.
When the CPU completes its current instruction, it tests the external interrupt latch.
If the interrupt latch is set and the interrupt mask in the condition code register is
reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt
latch while it fetches the interrupt vector, so that another external interrupt request
can be latched during the interrupt service routine. As soon as the interrupt mask
is cleared (usually during the return from interrupt), the CPU can recognize the new
interrupt request.
Figure 5-3
shows the sequence of events caused by an interrupt.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705J5A | 8-bit microcontroller units |
| MC68HC705K1 | HCMOS Microcontroller Unit |
| MC68HC705KJ1CDW | Computer Operation Properly Module |
| MC68HC705J1AVS | Microcontrollers |
| MC68HC705J1AVP | Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705J2CDW | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP |
| MC68HC705J2DW | 制造商:Motorola Inc 功能描述: |
| MC68HC705J5ACP | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC68HC705JB4DW | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC68HC705JJ7CDW | 功能描述:IC MCU 8BIT 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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