參數(shù)資料
型號(hào)： MC68HC908JK8CP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 32/56頁(yè)
文件大?。?/td> 648K
代理商： MC68HC908JK8CP
MC68HC908JL8SM/D
MC68HC908JL8MC68HC908JK8
SCI transmitter CPU interrupt request. In normal operation, clear the SCTE
bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets
the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data, preamble, or
break character is being transmitted. TC generates an SCI transmitter CPU
interrupt request if the TCIE bit in SCC2 is also set. TC is automatically
cleared when data, preamble or break is queued and ready to be sent.
There may be up to 1.5 transmitter clocks of latency between queueing data,
preamble, and break and the transmission actually starting. Reset sets the
TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register
transfers to the SCI data register. SCRF can generate an SCI receiver CPU
interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a
CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI receiver CPU interrupt
request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1
with IDLE set and then reading the SCDR. After the receiver is enabled, it
must receive a valid character that sets the SCRF bit before an idle condition
can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid
character must again set the SCRF bit before an idle condition can set the
IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR
before the receive shift register receives the next character. The OR bit
generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also
set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC908JK8MDWE 制造商:Freescale Semiconductor 功能描述:
MC68HC908JK8MP 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
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MC68HC908JL3CP 功能描述:IC MCU 8MHZ 4K FLASH 28-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC08 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤(pán) 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱(chēng):497-9032STM32F101T8U6-ND
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