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| 型號： | MC68HC908JK8CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 49/56頁 |
| 文件大?。?/td> | 648K |
| 代理商： | MC68HC908JK8CP |
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MC68HC908JL8SM/D
Condensed Electrical Characteristics
MC68HC908JL8MC68HC908JK8
3-Volt DC Electrical Characteristics
3-Volt Control Timing
3-Volt Oscillator Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VDD supply current
Run, fOP = 4MHz
(3), XTAL option
RC option
Wait, fOP = 4MHz
(4), XTAL option
RC option
Stop(5), –40°C to 85°C, XTAL option
RC option
IDD
—
3
4
1
2
0.5
0.3
8
10
4.5
6
5
2
mA
A
POR rearm voltage(6)
VPOR
0—
100
mV
POR rise time ramp rate(7)
RPOR
0.035
—
V/ms
Monitor mode entry voltage
VTST
1.5
× V
DD
—8.5
V
Pullup resistors(8)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
RPU
1.8
16
3.3
26
4.8
36
k
k
Low-voltage inhibit reset, trip voltage (no hysteresis)
VLVI3
2.18
2.49
2.68
V
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all
outputs. All ports configured as inputs.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0 V.
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency(2)
fOP
—4
MHz
RST input pulse width low(3)
tIRL
1.5
—
s
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Characteristic
Symbol
Min
Typ
Max
Unit
Internal oscillator frequency
fINTCLK
45k(1)
Hz
Crystal frequency, XTALCLK
fOSCXCLK
—16M
Hz
RC oscillator frequency, RCCLK
fRCCLK
2M
—
10M
Hz
External clock reference frequency(2)
fOSCXCLK
dc
—
16M
Hz
1. See Figure 55 for plot.
2. No more than 10% duty cycle deviation from 50%
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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