參數(shù)資料
型號： MC68HCL05C12AFB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 130/156頁
文件大?。?/td> 756K
代理商： MC68HCL05C12AFB
Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C12A — Rev. 3.0
General Release Specification
MOTOROLA
Serial Communications Interface (SCI)
75
NON-DISCLOSURE
AGREEMENT
REQUIRED
ILIE — Idle Line Interrupt Enable
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic ones from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic zeros. Clearing the SBK bit
stops the break codes and transmits a logic one as a start bit. Reset
clears the SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
相關(guān)PDF資料
PDF描述
MC68HSC05C12AFB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
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