參數(shù)資料
型號: MC68HCL05C12AFB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 143/156頁
文件大小: 756K
代理商: MC68HCL05C12AFB
Serial Peripiheral Interface (SPI)
SPI Registers
MC68HC05C12A Rev. 3.0
General Release Specification
MOTOROLA
Serial Peripiheral Interface (SPI)
87
NON-DISCLOSURE
AGREEMENT
REQUIRED
10.6.1 Serial Peripheral Control Register
SPIE — Serial Peripheral Interrupt Enable
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
Address:
$000A
Bit 7
654321
Bit 0
Read:
SPID
SPD
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
相關PDF資料
PDF描述
MC68HSC05C12AFB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
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